Laser thermal annealing (LTA) is used in semiconductor manufacturing for a variety of applications, including for activating dopants in select regions of devices (structures) formed in a semiconductor wafer when forming active microcircuits such as transistors and related types of semiconductor features.
One type of laser annealing uses a scanned line image from a light beam to heat the surface of the wafer to a temperature (the “annealing temperature”) for a time long enough to activate the dopants in the semiconductor structures (e.g., source and drain regions) but short enough to prevent substantial dopant diffusion. The time that the wafer surface is at the annealing temperature is determined by the power density of the line image, as well as by the line-image width divided by the velocity at which the line image is scanned (the “scan velocity”). The amount of time the line image resides over a point on the wafer surface is called the “dwell time.”
For some semiconductor device applications, there is a need to heat one side of the wafer while keeping the other side below a certain critical temperature. One example is a power device, where back-side dopant activation and contact is carried out after the front device is fabricated. Another example is a thin-substrate solar cell, wherein a highly conductive emitter is needed on the front side to improve the cell efficiency, and which can be achieved by doping and annealing. A third example is a back-side image sensor, where a field-stop layer that typically consists of highly doped and activated layers is used on the back side to suppress the dark current.
In all of these examples, there is a need for thermal annealing to activate dopants or form a contact on one side of the wafer. The substrate thicknesses involved are in the range of several to a few hundred micrometers (i.e., microns or μm), which is significantly thinner than the thickness of a standard 8-to-12-inch silicon wafer, namely, 725 μm to 775 μm. Typical dopant activation requires an annealing temperature above about 1,000° C. However, the maximum temperature and thermal budget for the other side of the substrate must be limited to avoid any potential degradation in material integrity and junction dopant profiles associated therewith.
For example, if metallization is already present on a first side of the wafer prior to laser thermal annealing, the maximum temperature of the first side needs to be kept below the melting point of the metal in order to maintain good physical integrity while the opposite (second) side is annealed.
Conventional rapid thermal annealing (RTA) has an annealing time on the order of seconds, which in silicon corresponds to a thermal diffusion length LD of several millimeters. This length is significantly greater than the typical wafer thickness, which means that both sides of the wafer will see similar peak annealing temperatures during RTA. Consequently, RTA is not suitable for such thin-wafer applications.
Conventional laser annealing methods for such thin-wafer applications involve using a pulsed melt laser with a pulse length in the range of tens to hundreds of nanoseconds. For silicon, this corresponds to a thermal diffusion length on the order of about 1 μm, which is significantly less than most wafer thicknesses. An advantage of pulse-melt annealing is that it can locally heat one side of a wafer to a very high temperature (including above the silicon melting temperature) with almost no heat penetration to the other side. Thus, it can be used for silicon wafers as thin as a few micrometers.
However, in the nanosecond time frame associated with pulse-melt annealing, dopant activation can be achieved only in the melted state. During melting, dopants can quickly diffuse and redistribute into a more box-like profile. While this may be advantageous for some applications, it may not be desirable in cases where precise doping profiles need to be maintained. In particular, the melting of multiple junctions can cause dopants of opposite polarities to intermix and degrade junction performance. A second limitation in the pulsed-melt annealing method is the depth of heat penetration. Because of the short thermal diffusion length, it is difficult to effectively anneal junctions deeper than 0.5 μm. Also, the method cannot be effectively used to anneal out implant defects beyond the melt depth due to the extremely low thermal budget associated with nanosecond-scale pulses.
Accordingly, there is a need for annealing thin semiconductor wafers that allows for efficient non-melt dopant activation on one side of the wafer without causing detrimental heating effects on the other side of the wafer.